/*
 * COM1 NS16550 support
 * originally from linux source (arch/ppc/boot/ns16550.c)
 * modified to use CONFIG_SYS_ISA_MEM and new defines
 */

#include <rthw.h>
#include <rtthread.h>

#include "dm368.h"
#include "uart.h"

#define UART_LCRVAL UART_LCR_8N1		/* 8 data, 1 stop, no parity */
#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS)		/* RTS/DTR */
#define UART_FCRVAL (UART_FCR_FIFO_EN |	UART_FCR_RXSR |	UART_FCR_TXSR)		/* Clear & enable FIFOs */

static void davinci_uart_init(davinci_uart_t port, rt_uint32_t baud_divisor)
{
	port->reg1.ier = 0x00;
	port->lcr      = UART_LCR_BKSE | UART_LCRVAL;
	port->reg0.dll = 0;
	port->reg1.dlh = 0;
	port->lcr      = UART_LCRVAL;
	port->reg4.mcr = UART_MCRVAL;
	port->reg2.fcr = UART_FCRVAL;
	port->lcr      = UART_LCR_BKSE | UART_LCRVAL;
	port->reg0.dll = baud_divisor & 0xff;
	port->reg1.dlh = (baud_divisor >> 8) & 0xff;
	port->lcr      = UART_LCRVAL; //select bank by seting LCR[7] = 0
	port->reg1.ier = UART_IER_RDI; /* lgnq Enable receiver data interrupt */
}

static int calc_divisor(davinci_uart_t port)
{
#ifdef CONFIG_APTIX
#define MODE_X_DIV 13
#else
#define MODE_X_DIV 16
#endif

	/* Compute divisor value. Normally, we should simply return:
	 *   CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
	 * but we need to round that value by adding 0.5.
	 * Rounding is especially important at high baud rates.
	 */
	return (CONFIG_SYS_NS16550_CLK + (115200 * (MODE_X_DIV / 2))) / (MODE_X_DIV * 115200);
}

struct rt_uart_dm368
{
	struct rt_device parent;

	davinci_uart_t uart_reg;

	/* buffer for reception */
	rt_uint8_t read_index;
	rt_uint8_t save_index;
	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
};

#ifdef RT_USING_UART0
struct rt_uart_dm368 uart0_device;

static void rt_uart0_handler(int vector)
{
	rt_ubase_t level;
    struct rt_uart_dm368 *uart = &uart0_device;

	rt_hw_interrupt_mask(IRQ_UARTINT0);

	if (uart->uart_reg->reg5.lsr & 0x01)	    /* Receive Data Available */
	{
		/* Receive Data Available */
        uart->rx_buffer[uart->save_index] = uart->uart_reg->reg0.rhr & 0xff;

        level = rt_hw_interrupt_disable();
		uart->save_index ++;
        if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
            uart->save_index = 0;
        rt_hw_interrupt_enable(level);

		/* invoke callback */
		if(uart->parent.rx_indicate != RT_NULL)
		{
		    rt_size_t length;
		    if (uart->read_index > uart->save_index)
                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
            else
                length = uart->save_index - uart->read_index;

            uart->parent.rx_indicate(&uart->parent, length);
		}
	}

	rt_hw_interrupt_ack(IRQ_UARTINT0);
	
	rt_hw_interrupt_umask(IRQ_UARTINT0);	
}
#endif

static rt_err_t rt_uart_init(rt_device_t dev)
{
	struct rt_uart_dm368 *uart = (struct rt_uart_dm368 *)dev;

    int clock_divisor;
	
	clock_divisor = calc_divisor(uart->uart_reg);
	davinci_uart_init(uart->uart_reg, clock_divisor);
	
	rt_hw_interrupt_install(IRQ_UARTINT0, rt_uart0_handler, RT_NULL);
	rt_hw_interrupt_umask(IRQ_UARTINT0);

	return RT_EOK;
}

static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
	struct rt_uart_dm368 *uart = (struct rt_uart_dm368 *)dev;

	RT_ASSERT(dev != RT_NULL);
	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
	{
		/* Enable the UART Interrupt */
//		NVIC_EnableIRQ(UART_IRQn);
	}

	return RT_EOK;
}

static rt_err_t rt_uart_close(rt_device_t dev)
{
	struct rt_uart_dm368 *uart = (struct rt_uart_dm368 *)dev;

	RT_ASSERT(dev != RT_NULL);
	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
	{
		/* Disable the UART Interrupt */
//		NVIC_DisableIRQ(UART_IRQn);
	}

	return RT_EOK;
}

static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
	rt_uint8_t *ptr;
	struct rt_uart_dm368 *uart = (struct rt_uart_dm368 *)dev;
	
	RT_ASSERT(uart != RT_NULL);

	/* point to buffer */
	ptr = (rt_uint8_t *)buffer;
	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
	{
		while (size)
		{
			/* interrupt receive */
			rt_base_t level;

			/* disable interrupt */
			level = rt_hw_interrupt_disable();
			if (uart->read_index != uart->save_index)
			{
				*ptr = uart->rx_buffer[uart->read_index];

				uart->read_index ++;
				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
					uart->read_index = 0;
			}
			else
			{
				/* no data in rx buffer */

				/* enable interrupt */
				rt_hw_interrupt_enable(level);
				break;
			}

			/* enable interrupt */
			rt_hw_interrupt_enable(level);

			ptr ++;
			size --;
		}

		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
	}

	return 0;
}

static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
	char *ptr = (char *)buffer;
	struct rt_uart_dm368 *uart = (struct rt_uart_dm368 *)dev;

	if (dev->flag & RT_DEVICE_FLAG_STREAM)
	{
		/* stream mode */
		while (size)
		{
			if (*ptr == '\n')
			{
				while ((uart->uart_reg->reg5.lsr & UART_LSR_THRE) == 0)
					;
				uart->uart_reg->reg0.thr = '\r';
			}

			while ((uart->uart_reg->reg5.lsr & UART_LSR_THRE) == 0)
				;
			uart->uart_reg->reg0.thr = *ptr;

			ptr ++;
			size --;
		}
	}
	else
	{
		while (size != 0)
		{
			while ((uart->uart_reg->reg5.lsr & UART_LSR_THRE) == 0)
				;
			uart->uart_reg->reg0.thr = *ptr;
	
			ptr++;
			size--;
		}
	}

	return (rt_size_t)ptr - (rt_size_t)buffer;
}

void rt_hw_uart_init(void)
{
	struct rt_uart_dm368 *uart;

#ifdef RT_USING_UART0
	/* get uart device */
	uart = &uart0_device;

	uart->uart_reg = (davinci_uart_t)DM368_BASE_UART0;

	/* device initialization */
	uart->parent.type = RT_Device_Class_Char;
	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
	uart->read_index = 0;
	uart->save_index = 0;

	/* device interface */
	uart->parent.init 	    = rt_uart_init;
	uart->parent.open 	    = rt_uart_open;
	uart->parent.close      = rt_uart_close;
	uart->parent.read 	    = rt_uart_read;
	uart->parent.write      = rt_uart_write;
	uart->parent.control    = RT_NULL;
	uart->parent.user_data  = RT_NULL;

	rt_device_register(&uart->parent,
		"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
#endif
}
